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AVija7
Novice
203 Views

Incorrect data at rx_dataout of stratix IV

Sir i designed the code for TX and RX using ALTGX,ALTRECONFIG in stratix IV. And successful at loopbacking, chip to chip communication.etc.

In real case we have transmitter designed by someone else. receiver designed by us in 2 different boards.

both are designed with:

1.Basic protocol

2.32 bit data

3.2500 gbps

When i connect both of them i'm getting random data at rx_dataout and sync is always high, error_detect and dispariy is fluctuating continiously never setting o zero. What i have to do sir??

 

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3 Replies
CheePin_C_Intel
Employee
96 Views

Hi,

 

As I understand it, you are observing the rx_errdetect and rx_disperr seems to be toggling while the sync status remains high. For your information, this seems to indicate that there are 8b10b errors detected at the received data. To facilitate further debugging, just would like to check with you if you have had a chance to tap rx_pll_locked and rx_freqlocked signals in signaltap? This will be helpful to tell if the CDR still remain locking to data or has already lost lock. 

 

In addition, signal integrity issue might lead to the 8b10b errors that you are observing. Just wonder if you have had a chance to check on the eye diagram at the SIV RX ball to see if it is still meeting RX spec in datasheet?

 

Please let me know if there is any concern. Thank you.

AVija7
Novice
96 Views

Sir,

I was able to receive the proper data, but with reverse order.

Earlier problem solved by providing the correct values for LOCK TO DATA, LOCK TO REF inputs.

 

Problem facing now:

I wanted to receive BC95B5B5 but receiving B5B595BC.

This happened when i gave "Word aligner pattern : 17C (K28.5)---10 BIT"

When i gave BCBC (5F17C) as control code, i lost sync

not only that im not sure about the exact control code.

For 10 bit we cant enable byte ordering block.

How to proceed sir??

 

 

 

Thanks and regards.

CheePin_C_Intel
Employee
96 Views

Hi,

 

As I understand it, your latest observation seems to be related to byte ordering issue. Would you mind to further elaborate on why you are unable to enable the byte ordering block?

 

Probably you can share with me your .ip or .qsys file of the Native PHY so that I can have a better understand of your configuration to further advice.

 

Thank you.

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