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Increasing the number of PCIe master address table entries

Altera_Forum
Honored Contributor II
827 Views

The PCIe master (avalon slave) uses a lookup table to generate the high address bits for the PCIe master cycle. 

This does let us convert non-contiguous host memory (eg allocated with Linux vmalloc()) into contiguous Avalon addresses. 

AFAICT this is just a internal memory block - so can have any (reasonable) size. 

However quartos 9.1 (I'm doing some experiments on an old project) only allows you to request table 512 entries, I'd really like 2048 entries (It only really makes sense to match the host page size of 4k). 

 

Does anyone know if this restriction is still present in the quartos 13 (or 14)? 

 

Or is there an easy way to edit the generated files (nasty I know) to increase the size. 

I think the size ends up as p_avalon_pane_count and uiPaneCount, editing the first might work. 

But I'd also need to change the Avalon slave addess map to increase the sizes of both slaves. 

 

Anyone managed to hack this? 

 

David
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Altera_Forum
Honored Contributor II
118 Views

The Address Translation Table Configuration option only supports up to maximum 512 address pages even in the latest Quartus II version.

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