Instantiating 2 JESD204B cores to interface with DACs. Fitter place errors on 8 TX : "Could not find path between source HSSI PMA Aux. block and the Transmitter channel."

[JCuel]

The first DAC instantiated with no issues. The second generates the fitter errors. I am targeting an Arria V 5AGXFB3H4F35I3 with two 8 Lane unbonded JESD204B cores. The cores are on either side of the chip.

[Nathan_R_Intel]

Hie,

I am suspecting this Fitter errors caused by incorrect Transmitter (Tx) channel placement in Pin Planner or Assignment Editor. For Arria V, we need to use one of the Tx channels as Tx PLL.

In a transceiver bank, either Ch1 or Ch4 can be selected as Tx PLL. Hence, for your device, there is twelve channels on one side. If all GXB_X0_CH1, GXB_X0_CH4 and GXB_X1_CH7, GXB_X1_CH10 is occupied, then this error could be observed.

Please change your Tx channel placement and check if the error is still observed.

Nathan

[JCuel]

I have a follow up questions. I have reduced the number of Lanes on my JESD204B core to free up a Tranceiver to be used as a Tx PLL. Specifically, I have reduced the JESD core from 8 to 6 Lanes but I also have 4 Lanes for an SFP+ interface. Do I need to use a Tx PLL for the JESD core and another for the SFP+ core? And, what are the external connections to the Tx PLL? Does my reference clock go to REFCLK1R or the Tx PLL (GXB_TX_R7 in my example below)?

Right: (B1R)

GXB_TX_R11 : DAC_JESD[0]

GXB_RX_R11 : Unused

GXB_TX_R10 : DAC_JESD[1]

GXB_RX_R10 : Unused

GXB_TX_R9 : DAC_JESD[2]

GXB_RX_R9 : Unused

GXB_TX_R8 : DAC_JESD[3]

GXB_RX_R8 : Unused

GXB_TX_R7 : Unused – (Reserved for JESD Tx PLL)

GXB_RX_R7 : Unused

GXB_TX_R6 : DAC_JESD[4]

GXB_RX_R6 : Unused

REFCLK3R : Unused

REFCLK2R : Unused

Right: (B0R)

GXB_TX_R5 : DAC_JESD[5]

GXB_RX_R5 : Unused

GXB_TX_R4 : Unused – (Reserved for SFP Tx PLL)

GXB_RX_R4 : Unused

GXB_TX_R3 : SFP_TX[3]

GXB_RX_R3 : SFP_RX[3]

GXB_TX_R2 : SFP_TX[2]

GXB_RX_R2 : SFP_RX[2]

GXB_TX_R1 : SFP_TX[1]

GXB_RX_R1 : SFP_RX[1]

GXB_TX_R0 : SFP_TX[0]

GXB_RX_R0 : SFP_RX[0]

REFCLK1R : DAC_JESD_REF_CLK

REFCLK0R : QSFP_REF_CLK

[Nathan_R_Intel]

Please check my replies to your questions in bold:

Do I need to use a Tx PLL for the JESD core and another for the SFP+ core? If both are running at different rates, then yes you need to use 2 Tx PLL.

And, what are the external connections to the Tx PLL? Does my reference clock go to REFCLK1R or the Tx PLL (GXB_TX_R7 in my example below)?​ Your reference clock only goes to the REFCLK pin as described in the Arria 10 Transceiver User Guide and Pin Connection Guideline. The reference clock will be routed from the pin to the Tx PLL internally.

Regards,

Nathan