Intel FIFO behave differently for M20K and MLAB memory configuration

[lingxi10]

Hi there,

I am building a project that uses DCFIFO. The write clock comes from PCIe with 125MHz and the read clock comes from PLL with 180MHz. The problem is when I am configuring the FIFO with M20K memory type, the very first data is unstable, meaning sometimes it gives the output of the second data and sometimes it gives the right output. The simulation is correct but the data in the physical board Stratix 10 is wrong. I used signal tap to go down to the writing and reading pointer of the FIFO and also the writing and reading data. The writing data is right but the reading data give the wrong result. However this doesn't happen why I instead use the MLAB memory to configure it.

For the timing constraint, I selected the "Generate SDC file and disable embedded timing constraint" to let the tool generate it automatically.

Can someone help? Thank you so much!

[Farabi]

Hi, 

Do you have test case project file so I can replicate the issue at my end ?

regards,
Farabi

[Farabi]

Hello, 

It is recommended for you is to use FIFO IP core generated from Quartus GUI (not from Platform Designer).
Then you can see the generated sdc file for the FIFO IP core and based on the file create your own SDC file for your custom-atom FIFO instances. Please aware that different configuration of FIFO may generate different SDC file.

regards,

Farabi

[lingxi10]

I am using the FIFO IP core generated from Quartus GUI. This problem was fixed by selecting the setting to make the aclr of fifo to be synchronized to both read clk and write clk. Thanks for the help