With the screenshot, it is hard to look on it and understand in full picture. Perhaps you should attach the platform designer file (.qsys).
By the way, you can look on the existing reference design (PCIe-DDR4) and compare it with your design?
Lastly, I can see you connect the emif_usr_clk to an IOPLL ref clock, this is looks like PLL cascading, I am wonder fitter allow you to pass the compilation?
What is the quartus version that you using? I am unable to open it, I think I need to use the same quartus version to open your qsys file.
Anyway, do you have a chance to look at the reference design? I think you should refer to the reference design first. Thanks.