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Altera_Forum
Honored Contributor I
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Interfacing SGDMA with custom component

I am using the "using triple speed Ethernet" with DE2-115 board tutorial, and trying to connect my own component directly to SGDMA using Q-sys. 

SGDMA is operating in stream to memory mode and my component is connected as a memory mapped slave to the m_write interface of the SGDMA. 

My component successfully receives data but there is a problem with synchronization; the "write" signal of the "m_write" interface is not being asserted with write operation. 

When I connect the same component to the nios2 data master as a memory mapped slave and write to its address It works perfectly fine.  

I have tried to find a timing diagram for the SGDMA to understand how the m_write interface works but could not find it. 

 

Thank you a lot
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