My device is an Arria 10 SOC. I'm using the GPIO Intel FPGA IP 18.0 core, set up as DDIO with separate input/output clocks. I'd like to use the clock enable (port), but I don't see whether that enable port is for the inclock or outclock.
I apologize for the late response,
When turning the Enable clock enable port ON, this allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
I hope this answers you r question, let me know if you need more help.
You may find more information regarding the port in our user guide here:
But there are 2 clock ports: clkin and clkout. In order for me not to violate setup and hold requirements, should the clken port be driven synchronously by the clkin or clkout clock?
For the GPIO input registers, the input I/O transfer will likely fail the hold time if you do not set the input delay chain.
For more info please read the Timing Closure Guidelines:
This last reply did not really address the question which is "should the clken port be driven synchronously by the clkin or clkout clock?". Can you please answer that question?
Steve Zack (the FAE supporting this customer)
The direction to the CKE is an INPUT.
This CKE will be controlling the CLK(clkin) of the IP.
If you are using BiDir(Bi Directional data), then you will have CK_IN(clkin) and CK_OUT(clkout), which the CKE will be controlling both of clocked in and out.