Issue with RSU module or corrupted flash?

[Jcole]

I have a RSU module in my boot-loader design running on the cyclone 10 LP eval board. I have a JIC file loaded with the boot-loader image at address 0x00, image 1 at address 0x400000, and image 2 at address 0x600000. Upon start up, the boot loader successfully loads and reconfigures the FPGA with image 1. 

Once Image 1 is loaded, its design is to run an exact copy of the the boot-loader statemachine, but this time pointed at address 0x00 (return to bootload).  An issue arises when the reconfig signal is pulsed, the board goes into an unresponsive state and even remains in this state during power cycles. To fix the board, I must program the FPGA with a new image file (Sof or Jic).

Any reason why the FPGA would become unresponsive?

[Fakhrul]

Hi Jcole,

Could you please refer to and try the example provided in the - Cyclone 10 LP Remote System Upgrade Design Example User Guide. The mentioned design example can be found here: Intel® Cyclone® 10 LP FPGA – Remote System Update Design Example

Also, note that to ensure the successful reconfiguration between the pages, assert the RU_nCONFIG signal for a minimum of 250 ns. This is equivalent to strobing the reconfig input of the Altera Remote Update IP core high for a minimum of 250 ns. If there is an error or reconfiguration trigger condition, the remote system upgrade state machine directs the system to load a factory or application configuration (based on mode and error condition) by setting the control register accordingly. You can refer to Intel® Cyclone® 10 LP user guide for more detailed information.

Regards,

Fakhrul

[Fakhrul]

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