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Honored Contributor I
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Issue with my FFT test "program"

Hey guys, I am new here on the board, but have been talking to some altera engineers about my issue but i dont wanna bother them too much so I decided to go here and see if you guys have any novel ideas. I am RELATIVELY unskilled at verilog. I took a uni class at UCSD about synthesizable verilog but we never programmed boards and the testbenches were written for us. Also, we never used megafunctions, but did use Quartus II 11.0. 

Now I am running a fully licensed copy of 12.0sp2. I am debating to go the DSP Builder route or the Qsys route, but the FFT core isnt in Qsys 

 

 

Ok guys, so I have initialized a couple megacore functions, including: 

PLL, 2 roms (1 single port, 1 dual), complex multiplier, and a ram where the result goes. 

 

Basically, I am learning in Verilog and need to create an entire system (debating whether to just go DSP Builder/Simulink way, if it's easier to get things to work and quicker). 

But I am writing this from scratch. 

I got a top level file that basically does the following: 

single port ROM (containing only real samples to be fft'd), and a register that is asserted zero for the imaginary samples for the fft. I am using a variable streaming FFT with 1024 taps, 16 bits of input precision, 18bit twiddle, 27bit output and Natural/Natural ordering, oh and fixed point. 

I am having trouble just getting data into the fft and then fed down the pipe. 

After the FFT, there should be the complex multiplier which multiplies samples of the incoming FFT'd samples with data contained in a dual port SRAM that is an inverse FFT'd impulse response of my off-board detector (dont worry about that, its just some data, 16 bits). Then, after the multiplication, which results in 36-bit output, I want to write this to onboard RAM and see it through SignalTap or ModelSim.  

 

I dont have a real testbench, but I force the clock to 100MHz (the freq the PLL expects) and trigger a reset. 

 

The problem is, I cannot get past the initialization state in my mealy FSM. I started with a Moore FSM with a single synchronous block. That didnt work so I tried now an asynchronous and synchronous setup. Where the synch part does reset, the address incrementing, turning on the comp_mult and basically "STATE <= NEXT_STATE" whereas my asynch machine has a case block for the combinational logic, like strobing sop, eop, getting the data set up, calling to increment addresses when necessary and all that. When I lok at it in ModelSim-Altera and signaltap, I get no data coming out of the FFT, and the FSM is stuck waiting for the fft's sink_ready signal. I have read the User Guide extensively and Avalon-ST interface and I think I should be doing things correctly, but I am having massive trouble. This has been a 3 week effort to get this damn thing working and I am asking for any pointers/help from you Verilog gurus out there. 

 

I did some modifications so my combinational logic isnt probably legit, but if someone could see if I am instantiating things properly and how do I get past the prep_fft stage. I know that there's only one check to see that if sink_valid==1 but that should be all I need right?
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