I am porting an endpoint PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues.
When using a test IP (xillybus) with ST-Avalon PCIE gen2 x8 and a correct pin assignement tooked from the exemple design provided wih the board I got this error messages in Fitter step:
Error(16400): Transceiver channel data signal < pcie_tx > is assigned to pin < PIN_BH45 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BL47 >.
Error(16400): Transceiver channel data signal < pcie_tx > is assigned to pin < PIN_BJ47 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BK49 >.
Error(16400): Transceiver channel data signal < pcie_tx > is assigned to pin < PIN_BG47 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_BH49 >.
Error(16400): Transceiver channel data signal < pcie_tx > is assigned to pin < PIN_AP45 >, but the specified pin is not compatible with the data signal. Assign the specified data signal to pin < PIN_AR51 >.
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
When I remove the PCIe TX assignement I get this error message:
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic pin in region (3, 30) to (3, 31), to which it is constrained, because there are no valid locations in the region for logic of this type.
Error(16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:
Error(184016): There were not enough differential input pin locations available (2 locations affected)
I attached the project if some one want to try.
Thanks a lot for your help
Hello, can you just follow the error message instruction to assign the pin accordingly? eg. Assign the specified data signal < pcie_tx > to pin < PIN_BL47 >.
You need to follow the error message instruction to assign all 16 pins accordingly.
Anyway, from the attached design, I found it already compiled successful. Is there some misunderstanding here? I guess the design is working previously. but after you changed something and you get the fitter error? if yes, please clarify what change that you did. 😃
Hello, Thank you for your answer.
The problem is the PIN_BL47 is for RX PCIe signal, not the TX, and it is the same as defined in the assignment of the example design qts_pcie_ep of the board and in the user guide ...
It's maybe a constraint to add or something?
I recompiled the project that I attached to be sure, and it stops in the Fitter step. Maybe it's due to the Quartus version, I use the Quartus Prime Pro 19.4 which one do you use for your compilation?
I didn't make a lot of modifications, I just change the FPGA to the one I have, regenerate ST-Avalon and reset release IP and change the assignments to the correct one for my board.
Yes, the design was made for a different board (also a stratix 10). I can send you the original version of the project if it help?
Maybe you can open the IP GUI (platform manager), generate the example design (top right corner), compile the example design without any location assignment and see if the fitter is pass.
I generate the example design and it compiles well, then I added the pin locations and I got the same error message (16400) then I permute RX and TX pin location and the design compile well. Is it correct to permute the TX and RX location ? in the example design of the board and in the documentation they didn't permute ... how PCIe would work if the TX became an RX and the RX a TX?
I also tried to permute the TX and RX in my original design, now I have only the Error(14566) and after
I don't think we can permute (I presume you mean swap) the TX and RX. Is there some misunderstanding? Can you list out you assign the Rx=? and Tx=? when there is fitter error?
This is the pin assignment that doesn't make errors (16400)
According to pin-out file, these assignment is the correct one and no need to swap.
PIN_BH45 is the RX pin = GXBL1C_RX_CH0p,GXBL1C_REFCLK0p
PIN_BL47 is the TX pin = GXBL1C_TX_CH0p
If you swap, you are permute it. So the error is expected.
Thank you :-)
This documentation need a correction then (page 31, 32 and 33): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-mx-devl-kit...
Can you tell me also please what reset do I need to use for PCIe EP because I have the same problem ...
What problem with the reset? I will suggest just follow the Quartus auto fit. Eg, compile the example design without location assignment and see it assign the rest to which pin. If you need further help, I hope you can create a new thread for this. It can help every single issue is track under independent thread. Ease the other to search if they are facing same issue.