Issues using ST-Avalon root port on Stratix 10 MX development Kit

[AKhel1]

Hello,

I am developing a root port PCIe IP on my Stratix 10 MX development kit (1SM21BHU2F53E1VG) and I have some issues.

When i compile my IP I got this error messages in Fitter step:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error(175001): The Fitter cannot place 1 I/O pad.

Info(14596): Information about the failing component(s):

Info(175028): The I/O pad name(s): pcie_rx_rc[0](n)

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:

Error(20196): Location(s) already occupied and the components cannot be merged. (1 location affected)

Info(175029): PIN_BH8. Already placed at this location: I/O pad pcie_rx_rc[0]

Info(175015): The I/O pad pcie_rx_rc[0] is constrained to the location PIN_BH8 due to: User Location Constraints (PIN_BH8)

In fact the error occures with the assignement of 7 pads :

pcie_rx_rc[0] PIN_BH8

pcie_rx_rc[2] PIN_BG6

pcie_rx_rc[3] PIN_BF8

pcie_rx_rc[4] PIN_BE6

pcie_rx_rc[5] PIN_BD8

pcie_rx_rc[6] PIN_BB8

pcie_rx_rc[7] PIN_BC5

When I remove this assignements the compilation is working well

I have the documentation of the board and the schematics and they give a different pin number for the pads ...

Thanks a lot for your help

Best regards

Amine

[User1573261788318367]

It looks like you used the same pin location for both of the differential pair signals. Double-check your pin-map. Generally the signal complement should be 1 pin away from the source signal.

[AKhel1]

Hello, thank you for your answer.

I already checked many times the Pin planner and the assignment editor, and each pin is declared only one time. Unfortunately the problème is not there ...

I also tried this workaround, but it didn't work for my board : https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2017/error--14566---the-fitter-cannot-place-1-periphery-component-s--.html

[AKhel1]

Can anyone give help me with my problem?

[HSuh01]

Check with your ".qsf" file. The chances are very little, but you may have some duplicated assignments in there. ".qsf" file has a kind of command line type pin assignment there. Hope it helps!

[AKhel1]

Thank you for your answer. I already checked this constraint file, unfortunately it isn't the source of my problems 😞

[User1573261788318367]

You should also double-check that the I/O standards are set correctly. For the PCIe pins generally the inputs should be CML and the outputs should be high-speed differential I/O.

[Nathan_R_Intel]

I believe you are running into a transceiver channel placement limitation. Could you check the following AN for guidelines. This following document list the limitation of Stratix 10 transceiver channel placement.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an778.pdf

Regards,

Nathan

[AKhel1]

Hello,

Thanks for your answers

@User15732617883183674336​  I tried with CML and high-speed differential I/O, same errors ...

@NathanR_Intel​ I read the documentation and for my board, I think every thing is ok. My errors happen in the fitter step for only 7 pins of 32.

I attache my project If some can help, I disabled the 7 pins that are generating errors. I use Quartus prime Pro 19.4 on Linux

Best regards,

Amine

[AKhel1]

Hello,

@NathanR_Intel​  Can you help me with my problem please ?

Best regards,

Amine

[Nathan_R_Intel]

Hie Amine,

Sorry for the delayed response. I have determined your issue. Please assign the p-n per the Stratix 10 MX development kit schematics. The HIP will detect the polarity is inverse and enable polarity inversion in the buffer. Your error is caused by placing the pin in the inversed location.

Please change as following:

pcie_rx_rc[0] PIN_BH7

pcie_rx_rc[1] PIN_BJ5

pcie_rx_rc[2] PIN_BG5

pcie_rx_rc[3] PIN_BF7

pcie_rx_rc[4] PIN_BE5

pcie_rx_rc[5] PIN_BD7

pcie_rx_rc[6] PIN_BB7

pcie_rx_rc[7] PIN_BC5

Regards,

Nathan

[AKhel1]

Hello @NathanR_Intel​ ,

Thank you very much, it works!

I don't understand one thing with these pins. I already developed PCIe interface with intel FPGA Stratix 5, Arria 10 and endpoint with Stratix 10 and I hade only to declare positive pins of PCIe and everything work.

Now if I use your solution I declare the 8 pins pcie_rx_rc[0] to pcie_rx_rc[7] by negative pins and the others by the positive ones.

I think there is maybe a mistake in the schematic for the root port.

Best regards,

Amine

[Nathan_R_Intel]

Hie,

PCie spec requires p-n inversion to be supported. Hence, inverting the pins is a supported feature to allow flexibility during PCB layout. Hence, its not a mistake, its just the schematics could be created that way for flexibility in the PCB layout.

Regards,

Nathan