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JESD204B deassembler

David32
New Contributor I
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I am using Arria 10 to receive data from multiple ADCs (the ADC09QJ800 from TI).

Each ADC device will be using JESD config as:

4 lanes

4 converters

8 bits per sample

The deassembler code generated by the Platform designer does not seem to support 8 bit samples (only 12-16 are allowed).

Am I supposed to write my own deassembler for this case?

Where does Intel publish information that could help me?

Thanks

David

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skbeh
Employee
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Hi David


The JESD204B IP does not incorporate the Transport Layer that controls the frame assembly and disassembly. The Transport Layer and test components are provided as part of a design example component where you can customize the design for different converter devices.

Hence customer need to build/modify per their use case.


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David32
New Contributor I
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Hi Skbeh,

 

I thought as much.

However I could not find any information on Intel site regarding the order of the data sent over the parallel interface from JESD204 receiver to the fabric. Without this information I cannot write my own disassembler.

 

Please direct me to the relevant data sheet or user guide where these details are written.

 

Thanks

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skbeh
Employee
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Hi David

The suggestion would be generate the JESD204B design example. Refer to the design example for the connection between transport layer and IP core.

Choose the closest allowable parameter values for generation. Modify the post-generated design parameters manually in the Quartus software to match your desire parameter settings.

The generated JESD design example has a transport_layer folder with 4 RTL files.


1) For information about the path data remapping in the Transport Layer.

Refer to https://www.intel.com/content/www/us/en/docs/programmable/683094/22-1/design-example-user-guide.html

For example Table 19, case M=4, S=1 where F=2, F2_FRAMECLK_DIV=2, user have to reorder the samples at application layer so it inputs correct data format to the transport layer and then generate expected Data Out as indicated in table below.


The data mapping in Table 19 jesd204_tx_datain[127:0]:

jesd204_tx_datain[127:0] = {{F14F15, F10F11,F6F7, F2F3}, {F12F13, F8F9,F4F5, F0F1}}

is equivalent to

jesd204_tx_datain[127:0] = {{M3S0, M2S0,M1S0, M0S0}, {M3S0, M2S0,M1S0, M0S0}}


2) Refer to section 'Customizing the Design Example' on page 50 of below user guide for more information about customizing the design example.

JESD204B Intel® Arria 10 FPGA IP Design Example User Guide

https://www.intel.com/content/www/us/en/docs/programmable/683113/


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David32
New Contributor I
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Hi Skbeh,

 

I really need a bit more help.

My design (with N = is not supported by the QSYS example designs.

In addition, the Transport Layer file generated by other QSYS example designs is not valid for N <12.

The IP core specific for my design outputs a bus of 128 bits.

All I want to know is the mapping of my samples into those 128 bits.

Please try and find an answer to this reasonable question.

 

Thank you,

David

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David32
New Contributor I
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Hi Skbeh,

 

I will try and be a bit more specific in my questions:

I know that the TL is not part of the core IP and that I must implement this.
Note that the example design does NOT cover my specific case of F=1, L=4, N=8, N'=8,  M=4, S=1.
 
I am asking how the received data is organized within the 128 bits parallel output of the core (rx_link_data).
 - for example, is it just simply 32 bits for each LANE?
The reason I need this answer is so that I can write my own transport layer and de-assembler code.
 
A few additional questions are:
 
I am using10 identical cores with parameters as above.
(Therefore I am using a total of 40 GXB Receivers).
The 10 identical ADC devices (each with M=4) are clocked synchronously from a central clock generator, although I do NOT require synchronous sampling.
The sample rate is 500 MSPS, meaning the line rate on each lane is 5G.
 
Is it sufficient to use a single core PLL within Arria 10 to supply the device_clk, link_clk and frame_clk to all 10 instantiations of the core IP?
This core PLL will have its reference synchronous to the JESD204 data stream of course.
 
Do you recommend Hard or Soft PCS for this case?
Any other recommendations for my specific case?
 
Thank you,
David
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