JESD204C - Reconfig XCVR Register Access

[Preethika]

We are attempting to access the JESD XCVR Reconfiguration registers via the HPS H2F interface.

We are able to successfully read from and write to the intended addresses. However, instead of receiving the full 16-bit readdata, we are consistently observing only an 8-bit readdata being returned from the JESD IP.

Please note that both JESD TX CSR and RX CSR Register accesses through HPS LW bridge were working as expected.

Brief description of the code snippets attached:

1. Register write to address 0x9003C
2. Register read from address 0x90040
3. Regardless of the register writes, we always receive the readdata as 0x65

Register description for these registers were not available in IP user Guide or in Register map document.

Could anyone please provide or point us to the documentation or details related to the JESD Reconfig XCVR registers?

This would help us better understand the expected behavior and usage.

[RongYuan]

Hi,

If you're looking for the F-Tile JESD204C Register Map files, maybe check below links:

https://www.intel.com/content/www/us/en/content-details/736791/f-tile-jesd204c-intel-fpga-ip-receiver-register-map.html

https://www.intel.com/content/www/us/en/content-details/736793/f-tile-jesd204c-intel-fpga-ip-transmitter-register-map.html

Regards,

Rong

[RongYuan]

The address 0x9003C and 0x90040 you're trying are not valid for the IP. Unfortunately, XCVR reconfiguration is not supported in JESD204C IP.

Regards,

Rong