FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6380 Discussions

JSED204B for Arria 10 SoC

User1580871742356367
423 Views

I've implemented JESD204B receiver in Arria 10 SoC, 10AS066N2F40. 

 

I got it working in JMODE0/2 at sampling clock 1600MHz and 3200MHz. So the line rate is 6400Mbps and 12800Mbps and rxlink_clk is 160MHz and 320MHz respectively. The sysref to the FPGA is 10MHZ in both cases. 

 

However I could not get link-up, no device aligned nor device sync with sampling clock at 3125MHz in same JMODE. Where the line rate is 12500Mbps, rxlink_clk is 312.5MHz and sysref is 3.90625MHz. 

I did check the clocks etc. and they are fine. 

 

Any suggestions? Hope to hear from you  ASAP. Thank you. 

 

 

0 Kudos
1 Reply
skbeh
Employee
402 Views

Hi


In your non-working case, sysref is 3.90625MHz. 

Few things you can check:


1) Sysref input must be provided to the JESD204B system. If have multiple links, each link will receive SYSREF pulse and initialize at the same time.

Page 63 of JESD204B User Guide-01142 stated that 

https://www.intel.com/content/www/us/en/docs/programmable/683442/21-3-19-2-0/link-startup-sequence.html

"...The IP core also ensures that at least one SYSREF rising edge is sampled before deasserting SYNC_N."


It means the SYSREF should be sent out few cycle before the SYNC_N (dev_sync_n) of the RX IP core can be deasserted.

There must be at least one SYSREF pulse detected before the dev_sync_n will goes high.

The dev_sync_n will never goes high if there are no SYSREF pulse detected at all.


You may refer to Figure 14 for the SYSREF & SYNC_N waveform. 


2) The dev_sync_n will never goes high if no SYSREF pulse is detected at all, it means the core will not come out of reset.

The SYSREF pulse should be issued while the core is in reset.

If the core misses the one SYSREF pulse that is sent, the core will remains in reset.


0 Kudos
Reply