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Altera_Forum
Honored Contributor I
1,467 Views

LDPC coder issues...

Hi, people! I'm attempt to simulate LDPC coder-encoder IP, set as wimedia 960-1320 

I make a testbench with data generator for simple counter 10 bit.  

I generate 96 word (960 bit) packet with start and stop pulses as per Avalon Streaming Interface directives... 

But encoder gives all outputs signals as undefined (!!!)  

Reset is active low, I release it after PLL locked. Ck is 100 mhz.. 

I try to force out ready = 1 and other issues but coder is always "broken"....  

Due to lack of documentation about this IP (very POOR) I haven't ideas to start up this ip...  

 

Attached here the testbench view and first simulation issue.. encoder input signals are ok (it seems so...) but encoder out is undefined (!) 

 

 

Have you meet similar issues with LDPC coder-dec simulation??
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7 Replies
Altera_Forum
Honored Contributor I
42 Views

During compilation, I find many of these warnings ...are all related to internal IP questions....  

 

Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "layer_E_sum" into its bus 

 

It is due to my device selection or other???
Altera_Forum
Honored Contributor I
42 Views

A UPDATE.. I see in modelsim, under UUT.. I see only my vinstantiated blocks, output encoder signals, but I don' see names of U_DEC and U_ENC blocks.... I read that is possible fully testing IP without license before purchasing..... It's possible that modelsim doesnt' allow to simulate LPDC IP blocks?

Altera_Forum
Honored Contributor I
42 Views

UPDATE II, I hope te be helpful for someone... 

I corrected QSYS enc,dec declaring on QUartus project and now Modelsim find the enc/dec models.. but Modelsim FAILS when read the encoder .sv file, finding a: 

Syntax error, unexpected non-printable character with the hex value '0x8b' (!) 

But this file .sv is unreadable... it is created from QSYS !! What's a bunch of confusion ... :-(
Altera_Forum
Honored Contributor I
42 Views

UPDATE III 

- Altera support doesn't run... :-( I attempt to fill all requested infos (job, mail etc but web page not upload the change and runs always with old data. 

- I send a service request but it is impossible to enter in my support, web page make an error "too many redirects"... I try to clean all cookies, I use 2 pc and a android phone : the result is the same "the page doesn't run" (!!!!!!!!!!!!) 

- I try these LDPC IP on a cyclonV dev kit.. well, without any support and any doc about coder and encoder.. 

* How I can set LLR and SOFT for decoder ??? It seem's decided from encoder , in some hidden manner. I found a _pkg.vhd file inside encoder directoris, and inside it there are LLR/SOFT decided when qsys create the ip (LLR=2,SOFT=3)  

* Well, I set decoder for LLR=2, SOFT=3, but data width input is fixed now to 6 and output is costrained to 2 (!!!)  

* I try to runs Enc + Dec on testbench running on Cyclone V E dev kit. I see with signal tap that Clocks, start/end of packet of 960/6 = 160 words are correct but the encoder doesn't live !!!!!!! Ready signals are 0, as per data out....  

 

 

IN MY HUMBLE OPINION, THIS IS NOT PROFESSIONAL ....WHY I MUST WORK WITHOUT ANY DETAILED TECH SPEC DOCS ABOUT THESE IP?????  

I must imagine parameters settings, behaviour and so on...  

 

(I WORKED WITH XILINX IP , DOC & SUPPORT WAS OF OTHER PLANET :-((((((((((
Altera_Forum
Honored Contributor I
42 Views

UPDATE IV after unlocking my account I have finally a response from ALTERA (Thanks to mr Chen) .. there is a bug on quartus... enc - dec libraries are call from modelsim twice (!) . I solved posing# comment on the twice lines over .do file and re-launch it from modelsim.. now it runs. Now there is the problem to understand coder - encoder behaviour without documentation.. (!!)) 

On my simulation, I generate a packet of 960 bit, word = 6 bit. Coder receive the eop/sop and the packet. Then it give in_ready=0 (ok..), after 7 clock cycles raises "out_valid" (ok).. but out data is all zeros (!!!!!). 

I try to change input data on rising or falling edge... nothing!  

Eop and Sop are pulses 1 cycle time, eop is on first packet word, sop is on last packet word.. But encoder doesn't run (!!!!) 

:mad::mad:
Altera_Forum
Honored Contributor I
42 Views

I redesign data test generator. Giving a 160 words, 6 bit each, Sop/EoP pulses rising edge on first and last data, CODER NOW RUNS.  

It generates 1320 bit in symbols 6 bit, with related SoP/EoP 

I give these data to decoder with all parameters (LLR,SOFT, PAR etc) set as per coder. 

Well, decoder runs, it gives a 2 bit streaming, total of 960 bit with SoP/Eop and out_valid asserted. Well, data are not coherent with input coder data.... I'm waiting for support... :-0  

Why documentation about these IP are so poor????
Altera_Forum
Honored Contributor I
42 Views

After Altera support explainations, Finally I can use and runs this IP... I spent 2 weeks trying and studyng... but wothout support explainations was impossible to run these box! ok... finished .... Support has solved a library compilation problem of these IP (yes.. a bug..) and then they give me how make some input decoder adjust to run correctly.. this is a lack of documentation!!!!!!

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