i want to use LPM DIVIDE in max 10, and i use quartus prime 16.1, the clk is 96MHz
but i did not found information about the latency of LPM DIVIDE , so i do not know how many clks should i wait to get the right outputs
Usually, what we do is use the modelsim to simulate the RTL behavior of the design first.
Then constrain the design and make sure the timing closed.
From there, you should be able to see the latency in the Timing reports.
This latency should not be vary so much. If you look into the modelsim simulation, you will see usually, it take about one cycle of input clock to do the operation.
What I try is simulate your design in the rtl simulator vwf files. I dont see any output, can you try it on your side? You can bring out the *vwf files with file -> new -> vwf files.
You dont need to set the multicycle path for now, after you make sure your rtl simulation behavior, only you set the multicycle.
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