Hello,I'm planning to implement a kind of ethernet-to-parallel data link using a 3C120 dev kit. The idea is to get the data from ethernet, using something similar to the UDP off-load example, put it in a big FIFO using one of the DDR RAM blocks of the 3C120 dev kit, and output it as 8-bit parallel data synchronized with a 30 or 40 MHz clock. Since the transfer rate must be continuous and sustained, a 128MB sized FIFO would hold around 3-4 seconds of data. I'm looking for advice on what would be the best approach to implement this, if using some of the avalon streaming IPs (SGDMA memory-to-stream?) that looks to me a bit complex although powerful, or if a simpler approach could be used? Thanks!
Actually this should be easier to implement than trying to use DMAs to do it. Really all you need is a master that keeps track of a read and write address independently and makes sure they the addresses never cross. You would implement the counters to be modulo so that they can roll over and start at the beginning of the memory where appropriate. I would also use some on-chip memory FIFOs to buffer between the master and the streaming inputs and outputs of the FIFO block.So for the FIFO input I would do something like this: ST Data Input (sink) --> Onchip FIFO --> Write Master (to SDRAM) For the FIFO output I would do something like this: Read Master (from SDRAM) --> Onchip FIFO --> ST Data output (source) Those Onchip FIFOs allow you to use the empty/full signals to implement ST flow control and isolates the master logic from the streaming logic. I hope that makes sense.
Thanks! This is more or less that I was thinking on... also to use on-chip FIFOs to help flow control, but I'm not too much fluent with avalon buses.Well, probably I will come back when starting to implement it and trying to make it work :) Regards
Up on www.altera.com is a design example called the "Master Templates". You could take a look at those to learn more. Some of the logic you will not need since your addressing scheme doesn't need to be as complicated. Since the new DDR SDRAM controllers don't require bursting to be efficient I would recommend creating a non-bursting read/write master since it's a little bit easier to implement.