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5877 Discussions

MAX10 Development kit LVDS TX assignments

Altera_Forum
Honored Contributor I
785 Views

I'm currently using the MAX10 development kit, and I'm trying to interface with two external components. 

In order to have a stable clock circuit, I use the "external" clock source on the MAX10 Development kit, and run it trough a PLL on the FPGA to derive different clocks. 

Now, I want to output some of these clock signals using the HSMC_CLK_OUT_n/p[1,2] signals. 

 

Ideally I want the clock frequency to be at 50MHz, but I've been unable to create stable signals on the output pins of unless I tune the clock down to 8MHz. I've checked the assignments, and the pins themselves are assigned to LVDS, so from what I can gather the FPGA should be able to handle 50MHz switching? 

 

My current signal path is this External_CLK => SRCCLKPLL => ALTERA_GPIO_LITE => Output_pin.  

 

Do i need any additional blocks internally on the FPGA? Am I going about this the right way, or is there a simpler way to get a stable, synced clock output off the MAX10 devkit?
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Altera_Forum
Honored Contributor I
110 Views

Your path looks fine to me. But it looks like those HSMC_CLK_OUT outputs take a straight shot to the HSMC connector. Do you have anything plugged into the HSMC slot that terminates the clocks? LVDS doesn't work very well when not terminated. 

 

If you can't terminate the clocks then try a single-ended output standard, such as LVCMOS. LVCMOS should be able to run at 50MHz no problem.
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