FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
6153 Discussions

MAX10, Reading and Writing to the flash

Altera_Forum
Honored Contributor II
1,034 Views

Tools> Qsys > Basic Functions > On-chip Memory > Altera Onchip Flash 

 

It will generate the verilog files once you go through selecting how you would like to configure the flash.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
121 Views

Altera has put several videos on YouTube about the MAX 10. Several deal with the flash. Essentially, you add a component for it to your QSYS system. It is particular to the MAX 10.

Altera_Forum
Honored Contributor II
121 Views

The video says to use the Quartus GUI to add Avalon-MM but it gives no instruction as to how one goes about actually creating and incorporating the module.

Altera_Forum
Honored Contributor II
121 Views

Both Altera and Terasic have videos on how to use QSYS. I've seen them with QSYS as the top level module and with QSYS integrated with other modules. They were made for FPGAs but the process is the same for the MAX 10, you just need to use the MAX 10 flash component.  

 

There are also step by step written instructions available on the Altera web site.
Altera_Forum
Honored Contributor II
121 Views

Do you have a link to the video/step by step instructions?

Altera_Forum
Honored Contributor II
121 Views

I was able to get the ip core in my file

Reply