Hello ,
The problem I have with DDR3 memory .I have Cyclone V and memory MT41K128M16-107 , it is an external system with a different processor .
With Semiconductor intellectual property core utilizes a block DDR3 . Dating I set parameters according to the Documentation.
PLL_REF_CLK - 100
MHzMemory clock speed - 300 MHz
PLL reference clock frequency - 100 MHz
Here I have a question I have a problem because I get the data from the frequency of 80 MHz , but Controller moments together draws me because waitrequest filled TO buffer .
I have to use FIFO with a record of 80 MHz and read to do a level of 45 MHz - then the IS OK.
mp_cmd_clk - set to 45 MHz .
Why I can not write / read at a frequency of 80 MHz ?
