FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Memory bandwidth width SDRAM and VIP

Honored Contributor II



I have a design with a DE2 board and a PSP LCD to display an image! 


The FPGA connected to the LCD has one SDRAM chip connected. For my implementation uClinux needs to run on the NIOS/SDRAM. The LCD frame buffers (2) also need to be stored in the SDRAM chip. The capacity of the SDRAM chip is large enough to hold the uClinux footprint and the two LCD buffers.  


I think I will have a problem with my memory bandwidth. But this is a bit of a gamble. The pixel clock frequency is 8 MHz, color depth bpp (pixel/memory) is 32 (clocked video output). At this moment the NIOS, SDRAM and Frame reader are running at 80MHz. 


uClinux will also run from the same SDRAM as the Frame Reader. Therefor I think I have a problem. I'm not quite sure how to calculate the memory bandwidth and see if I have a problem.  


Sorry if my English a bit vague. 


Thanks :)
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