I am simulating the PCIe endpoint design example generated by the Altera PCIe compiler. This is the Chaining DMA design that comes with PCIe rootport testbench. Normally the testbench writes to the chaining DMA memory mapped registers starting at address 20000. It specificallly writes 0003_0003 at address 20010. I performed a DW read at address 20010 and the chaining DMA exmple returned 0003_0003 correctly. Then I issued a read at address 20000 with DW data length of 32 DWs but the data returned for this transaction is all zero. I was expecting 0003_0003 in 20010. I am not sure if the chaining DMA allows more then one DW read. Any comments?
