Modelsim error on alt_dual_boot and altera_onchip_flash_block - Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.

[AFahr2]

Hello all,

I'm trying to simulate a simple SPI - Flash interface using:

• Spi_Slave
• Avalon bytes to packets and Packets to bytes
• Packets to master
• Onchip Flash
• Dual Boot
• Clk

I'm using the Lite edition of Quartus 18.1, Platform Designer 18.1 and ModelSim - INTEL FPGA STARTER EDITION 10.5b.

I can generate the code with platform designer and compile it with Quartus. I have a testbench file to simulate the SPI interface. I have followed the instructions on "Simulating in ModelSim-Altera Edition usingNativeLink" (https://www.intel.com/content/dam/altera-www/global/en_US/kdb/rd10312011_847/nativelink_simulation.pdf) and that all has worked out well. I can start the simulation using "Tools -> Run Simulation Tool -> RTL Simulation".

When the simulation starts, I get following errors on the ModelSim output:

** Error: (vsim-3033) d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash.v(309): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.

#   Time: 0 ps Iteration: 0 Instance: /spi_flash_tb/DUT/u0/onchip_flash_0 File: d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash.v

Error: (vsim-3033) d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_dual_boot.v(41): Instantiation of 'alt_dual_boot_avmm' failed. The design unit was not found.

#   Time: 0 ps Iteration: 0 Instance: /spi_flash_tb/DUT/u0/dual_boot_0 File: d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_dual_boot.v

What I've tried so far:

• Removing the Onchip Flash and Dual Boot IPs from Qsys: Everything works well, but without the flash and dual boot functionality.
• Adding alt_dual_boot_avmm.v and altera_onchip_flash_block: These files are within the folders as encrypted files, I could not find a way to link them into Modelsim by changing my simulation.do file in the modelsim folder.

At this point, any help would be greatly appreciated, or workaround as well.

Thanks,

Albert F.

[Kenny_Tan]

Hi,

Can you used:

do <design_name>_run_msim_rtl_vhdl.do

Look into the .do files what simulation model is needed.

Thanks,

Best regards,

Kenny

[AFahr2]

Hi Kenny, thanks for your reply.

I actually do use "do spi_flash_run_msim_rtl_vhdl.do", which is generated by Quartus I believe.

That's when I get the error message. The file "do spi_flash_run_msim_rtl_vhdl.do" looks like this (sorry if this is a bit long):

transcript on

if {[file exists rtl_work]} {

   vdel -lib rtl_work -all

}

vlib rtl_work

vmap work rtl_work

vlib rsu_test

vmap rsu_test rsu_test

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_avalon_packets_to_master.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_avalon_st_bytes_to_packets.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_avalon_st_packets_to_bytes.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_dual_boot.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash_avmm_csr_controller.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash_avmm_data_controller.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_onchip_flash_util.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_reset_controller.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_reset_synchronizer.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_avalon_st_adapter.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_avalon_st_adapter_001.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_avalon_st_adapter.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/spiphyslave.v}

vlog -vlog01compat -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_avalon_sc_fifo.v}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_arbitrator.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_burst_uncompressor.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_master_agent.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_master_translator.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_slave_agent.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_slave_translator.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/altera_merlin_traffic_limiter.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_avalon_st_adapter_001_channel_adapter_0.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_avalon_st_adapter_channel_adapter_0.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_cmd_demux.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_cmd_mux.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_router.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_router_001.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_rsp_demux.sv}

vlog -sv -work rsu_test +incdir+d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules {d:/projects/vhdl/spi_flash/db/ip/rsu_test/submodules/rsu_test_mm_interconnect_0_rsp_mux.sv}

vcom -93 -work work {D:/Projects/VHDL/spi_flash/spi_flash.vhd}

vcom -93 -work rsu_test {d:/projects/vhdl/spi_flash/db/ip/rsu_test/rsu_test.vhd}

vcom -93 -work work {D:/Projects/VHDL/spi_flash/spi_flash_tb.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -L rsu_test -voptargs="+acc" spi_flash_tb

add wave *

view structure

view signals

run -all

As mentioned before, the project compiles ok, but there's the errors above on the simulation. I tried linking and adding both missing files (which are in the /rtl subfolders) to no avail.

I'm happy to upload the project if that helps you replicate the error.

Thanks,

Alberto

[Kenny_Tan]

Sure, you can attached your design.qar file for me to have a look.

[AFahr2]

Hi Kenny,

thanks, the file is attached. The main file is spi_flash.vhd, and the testbench is spi_flash_tb.vhd. The .qsys file should be under the rsu/rsu_test folder.

If you have any questions or suggestions, let me know.

Thanks,

Albert F.

[Kenny_Tan]

Thanks, I manage to look into it.

Since the design are from qsys, what you need to run is msim_setup.tcl. You may follow the steps below:

1) Open up the qsys files, generate the simulation model, generate -> generate hdl

2) Open modesim, cd to directory where the msim_setup.tcl

source msim_setup.tcl

3) ld

4) now the modelsim success run the simulation.

to include the tb

5) open up the msim_setup.tcl and modify the top level to spi_flash_tb

6) make sure your spi_flash_tb.vhd spi_flash under vcom

7) ld again.

Let me know if you do not get it,

Thanks

[AFahr2]

Kenny, thanks for your answer, it took me a while but I got it in the end.

Just for the sake of completion if anyone runs into the same issues:

• The msim_setup_tcl file is located under /simulation/mentor
• I replaced the original testbench file with my "spi_flash_tb.vhd" file on this line: "set TOP_LEVEL_NAME "spi_flash_tb" "
• I added the following lines under vcom, at the end, in this order:

 eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS       "$QSYS_SIMDIR/rsu_test.vhd"

 eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS       "$QSYS_SIMDIR/spi_flash.vhd"

 eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS       "$QSYS_SIMDIR/spi_flash_tb.vhd"

Otherwise the test simulation was missing some blocks.

• Ran the following commands:

quit -sim

source msim_setup.tcl

ld

and it all seems to compile now. I'll test it for a while now, but it seems the issues I was having are resolved.

Thanks kindly for your support!

Cheers,

Albert F.

[Stephanie]

Hi Albert I'm running into the same issue as you, what does your altera_onchip_flash_block.v look like? Mine is a hex file it seems...