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Hello.
I'm trying to simulate project with getting data from OnChipFlash.
I'm using the Lite edition of Quartus 17.0.2 and ModelSim - INTEL FPGA STARTER EDITION 10.5b.
I create testbench file to simulate the project. I start the simulation using "Tools -> Run Simulation Tool -> RTL Simulation".
When the simulation starts, I get following error on the ModelSim output:
** Error: (vsim-3033) c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /AC_main_tb/main_inst/sin_data/onchip_flash_0 File: c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v
When I comments the OnChipFlash module everything works well, but without extracting data from flash.
File altera_onchip_flash_block.v do not opened, because is encrypted file.
I find similar post on forum:
I tried to perform the actions as written in the post above with the substitution of my names:
1) Open the qsys files, generate the simulation model, generate -> generate hdl
2) Open modesim, cd to directory where the msim_setup.tcl
source msim_setup.tcl
3) ld
4) open the msim_setup.tcl and modify the top level from "OnChipFlash" to "AC_meas_tb"
6) add the following lines under vlog in "alias com" section, at the end, in this order:
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/main.v"
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/AC_meas_tb.v"
7) ld again.
I get following error:
Error: (vlog-7) Failed to open design unit file "./..//main.v" in read mode.
# No such file or directory. (errno = ENOENT)
If I start simulation using "Tools -> Run Simulation Tool -> RTL Simulation" I get error Error: (vsim-3033) .....altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
At this point, any help would be greatly appreciated, or workaround as well.
Thanks, Aleksey
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You make the AC_meas_tb as the testbench. Can you check inside the AC_meas_tb.v files, what is your module name there? currently, the tools are complaining the testbench issue.
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Can u open a new thread on this? this seem to be different issue from the original one.
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I found the answer why FFFFF is always read from flash memory. The answer is simple: I always used a SOF file for programming, but when flash memory is used, I need to program a POF file.
PS: I apologize for such a long feedback
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