FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5989 Discussions

question about lpm_divide pipeline ?

zlan01
Beginner
288 Views

I am implementing a project using max10 and using lpm_divide, but when I set the output delay parameter, the area occupation is still 87%, in my thought when I set the output delay parameter to 4, the area occupation should be 1/4 of the original area? what is the function of the pipeline parameter?

0 Kudos
4 Replies
KhaiChein_Y_Intel
186 Views

Hi,

 

The LPM_PIPELINE specifies the number of Clock cycles of latency associated with the quotient[] and remainder[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinational function will be instantiated. If omitted, the default is 0 (non-pipelined). You cannot specify a value for the LPM_PIPELINE parameter that is higher than WIDTH_Q.

and the PIPELINE_DELAY shifts the placement of the pipeline registered stages. By default, WIDTH_Q/2 starts at the middle stage. Specify 0 to start at the last stage. Specify WIDTH_Q-1 to start at the first stage. The default value is WIDTH_Q/2.

 

Thanks.

Best regards,

KhaiY

zlan01
Beginner
186 Views

the key is that the logic resource is not engouth for my project, generally we can using time to save the usage of the logic resource. can we do that using the LPM_PIPELINE parameter , or the LPM_PIPELINE parameter just delay the output ,but the divider is still a pure combinational logic, and the area occupation will not decrease , and it always keep the same area occupation for the lpm divider although the LPM_PIPELINE parameter is value bigger than zero ?

KhaiChein_Y_Intel
186 Views

Hi,

 

I tried to create two LPM_DIVIDE, one with pipeline 3 and one with no pipeline. The ALM used in the design with pipeline is more than the design with no pipeline. You may check this in the Resource Usage Summary.

 

Thanks.

Best regards,

KhaiY

KhaiChein_Y_Intel
186 Views

Hi,

 

Do you have any updates?

 

Thanks.

Best regards,

KhaiY

Reply