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Altera_Forum
Honored Contributor I
777 Views

Modify Ariia V ALTLVDS_TX data rate during work

Hello everyone, 

I'll try to explain the issue as clear as I can. 

I have a block which can operate at 2 different clock rates : 162 MHz and 270 MHz. 

I need to use ALTLVDS_TX with serialization factor of 10 ,which can support the 2 clock rates (1620 Mbps or 2700 Mbps). 

 

suppose that I use a PLL which generates the 2 clocks ( 162 MHz and 270 MHz) and switch them using Altera clock mux. 

What is the best to make a configurable ALTLVDS_TX that can change data rates at command? 

 

Thanks in advance
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8 Replies
Altera_Forum
Honored Contributor I
47 Views

The Arria V dedicated LVDS hardware does not have access to the clock mux. It uses a dedicated clock path from the LVDS block to the LVDS channels. Three clocks are used too, one for high-speed serial, one for the parallel clock, and one as a clock enable to load data between. You'll want to create the altlvds with an external PLL and then reconfigure that PLL. (I haven't fully checked if you can reconfigure it when in LVDS mode, but I assume so).  

 

That's all if you're using altlvds. I thought 162 and 270 were your serial rates, but rereading, your serial rates are 1620 and 2700 Mbps. altlvds doesn't run that fast and you'll need high-speed serial I/O.
Altera_Forum
Honored Contributor I
47 Views

Thank you for the quick reply! 

Just to clarify something. I'm thinking of using a "master PLL" to generate 2 clocks : 162 MHz and 270 MHz for the logic blocks. 

 

those 2 clocks will go through ALTCLKCTRL and only one will act as the system clock .  

 

1.Can I use this clock as reference clock of the ALTLVDS PLL? (which in turn will produce x10 serial clock) 

2.What do you mean "high-speed serial I/O" ? (is it an IP i can instantiate ) 

 

Thanks again
Altera_Forum
Honored Contributor I
47 Views

Are you trying to send data out at 1620 Mbps and 2700 Mbps, while inside the FPGA you have 10 bit words of 162Mbps or 270 Mbps? If so, LVDS doesn't run that fast and you need a higher speed protocol(which has overhead). 

 

Or are you sending out data at 162Mbps or 270 Mbps? If that's the case, you probably don't even need altlvds and can build it out of logic. 

 

(A third option is that your sending data out a 324Mbps or 540Mbps, as people often send data at double-data rate) 

 

I don't have a sense of what you're doing. For the idea of sending a different reference clock to the altlvds block, probably not. Note that altlvds in Arria V has a PLL in it. By default it's instantiated inside(although you can change this so the PLL is external and you have to manually create it and hook it up). The PLL probably can't take an input frequency range that is that high, although I'm not sure.
Altera_Forum
Honored Contributor I
47 Views

"Are you trying to send data out at 1620 Mbps and 2700 Mbps, while inside the FPGA you have 10 bit words of 162Mbps or 270 Mbps?" 

This is exactly the case! :) 

 

If LVDS won't work , what solution do you suggest?
Altera_Forum
Honored Contributor I
47 Views

Hello all, I am trying to constrain my ALTLVDS design on Cyclone V which is using the same SERDES as ARRIA V. I get littre channel to channel skew and I want to correct it. In the fitter report there is the LVDS receiver package skew compensation and the LVDS Transmitter Package Skew Compensation. How to add the trace delay addition recommended in those report ? I didn't find any hints on the web fix it.  

 

Thank you for your help.
Altera_Forum
Honored Contributor I
47 Views

What device are you talking to that's running that fast? I pretty much never see any devices that go above 1Gbps(maybe 1.25 Gbps) for LVDS, and the DACs and ADCs that did do that are all moving to JESD204B and multi-gigabit transceivers, as LVDS just couldn't handle it. FPGAs top out at 1.6Gbps, but that uses some special stuff on the receiver, like Dynamic Phase Alignment. I can't imagine a device with a spec that requires 2.7Gbps LVDS. 

If you're talking FPGA to FPGA, make it wider(you didn't say how wide the bus is, so if it's 1 bit then definitely make it wider). Heck, make it a 10-bit bus and just send it all in paralllel. 

If you need gigabit transceivers, you're going to need a protocol, but whatever you're talking to should already have that defined. 

http://www.altera.com/devices/fpga/arria-fpgas/arria-v/transceivers/arrv-transceivers.html 

http://www.altera.com/literature/hb/arria-v/av_5v3.pdf
Altera_Forum
Honored Contributor I
47 Views

I'm implementing DisplayPort protocol and it requires 1.62/2.7 Gbps differential pair .That's why I though of LVDS

Altera_Forum
Honored Contributor I
47 Views

DisplayPort is a much larger protocol that just the data rate. Altera has a core, but I don't know the details. 

http://www.altera.com/products/ip/iup/video/m-alt-displayport-megacore.html 

http://www.altera.com/literature/ug/ug_displayport.pdf
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