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MultiChannel Serdes on CycloneIV GX problems

Honored Contributor II

Hi all, 

I met a problem about multichannel(> 4 ch) serdes design on CycloneIV GX fpga.the generated ALT_GX megacore's source file include a 2-bit width pll_iclk signal,so I connect the 2-bit signal to 2 pins.but,after compile,I found that QuartusII warning says:  



Warning: Design contains 1 input pin(s) that do not drive logic 

Warning (15610): No output dependent on input pin "ref_clk[1]" 



I'v connect eight data generate module and a alt_reconfig module to the alt_gx module ,so I think maybe somethins wrong? 





I attached the test project,hope somebody can help me.
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