I am upgrading a Qsys system from a Stratix V to Arria 10; both using DDR3. For the Stratix V system there are two DDR3 SDRAM Controllers with UniPHY, one for the master and one for the slave. These core are not available to the Arria 10 so I am using the Arria 10 External Memory Interface core which has a core clocks sharing parameter that can be: No Sharing, Master, or Slave. I was wondering if by selecting the No Sharing option would it then be possible to use only instantiation of the core and have it act the same as the two cores did in the Stratix V system.
