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Honored Contributor I
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Multiple Avalon-MM Master connected to DDR2 SDRAM Controller

my design: 

 

I made my design on Qsys. I have multiple components with (Avalon-MM Master) connected to the same (Avalon-MM Slave) of DDR2 SDRAM Controller with UniPHY . My components are:  

 

* 3 Frame Buffers (read master and write master) 

* 2 SGDMA 

* 1 Nios II Processor (data master and instruction master) 

 

Number of masters are: 10.  

Nios program loaded into ddr2. Each frame buffers has different base addresses. 

 

my questions: 

 

* Is my connection with ddr2 correct ? Is there a better connection for better performance and bandwidth ? 

* How to choose frame buffer base addresses ?  

* How to know the origination and occupation space for ddr2 ? 

 

Please advice me in my design.
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