Honored Contributor II
09-07-2013 09:30 AM
my design:I made my design on Qsys. I have multiple components with (Avalon-MM Master) connected to the same (Avalon-MM Slave) of DDR2 SDRAM Controller with UniPHY . My components are: * 3 Frame Buffers (read master and write master) * 2 SGDMA * 1 Nios II Processor (data master and instruction master) Number of masters are: 10. Nios program loaded into ddr2. Each frame buffers has different base addresses. my questions: * Is my connection with ddr2 correct ? Is there a better connection for better performance and bandwidth ? * How to choose frame buffer base addresses ? * How to know the origination and occupation space for ddr2 ? Please advice me in my design.