Multiple transceiver design

[FCald4]

Hi, I'm using an arria 10 device that as 36 transcievers and I'm trying to implement a design using 24 of them in this way:

-3 xaui using ip

-8 transcivers with configurable speed 1/2,5/10Gbps using the ethernet ip that let implement reconfigurable transceivers

-4 transcivers at fixed speed 2,5Gbps using same ip used for reconfigurable transceivers but with a fixed speed of 2.5G

I'm trying to use a shared fplls (3, one for each speed) for transceivers with selectable speed, 1 fpll in common for the transceivers at 2.5G and 1 atx pll for each xaui but the fitter is failing in finding a location for all plls even if the number of available plls is higher than the one used (no user assigned location/pins, trying to let quartus manage all placements). The error code is : Error (14996): The Fitter failed to find a legal placement for all periphery components

First of all I want to understand if the sat of transceivers that I'm trying to use is feasable in this device. Then I want to know if there'a a guide to follow for this kind of implementation.

[CheePin_C_Intel]

Hi,

As I understand it, you have some inquires related to the TX PLL placement. To facilitate further debugging, it is recommended for you to create simple test design with only Native PHY instances mimic the configuration used by the IP ie data rate, bonding, refclk and channel placement. This would help to isolate out IP dependencies ie TSE, XAUI from the debugging. You may start with simple design ie one x4 Native PHY, then slowly add on more modules and test the compilation. This will be helpful to narrow down when the error start to pop up. Please feel free to share with me the Native PHY only test design which is able to replicate similar placement error so that I could further look into it.

Please let me know if there is any concern. Thank you.