FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

My first attempt

Altera_Forum
Honored Contributor II
926 Views

Hi try create simply custom component. In the pdf altera avalon specification is described MM slave. I wrote this vhdl(very simply, i try learn add component): 

 

entity MyCustom is 

port 

clk : in std_logic; 

wr : in std_logic; 

write_data : in std_logic_vector(7 downto 0); 

reset : in std_logic; 

 

-- conduit 

led: out std_logic_vector(7 downto 0) 

); 

end MyCustom; 

architecture pokus of MyCustom is 

begin 

process(clk,reset) 

begin 

if (reset='0') then 

 

led<="00000000"; 

elsif(clk = '1' and clk'event)then 

 

if(wr = '1')then 

led <= write_data; 

else null; 

end if; 

end if; 

end process; 

end pokus; 

 

signal from entity are the same like on example in the pdf. 

i wanna only write values to output. C code is this: 

# include <stdio.h> 

# include <system.h> 

# include <io.h> 

 

int main() 

 

IOWR(0x00011018,0,0x0f); 

 

return 0; 

 

But it doesnt work, is that wrong way? 

 

Thanks, Vaclav
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Altera_Forum
Honored Contributor II
193 Views

0x00011018 this the base address of my component from SOPC

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Altera_Forum
Honored Contributor II
193 Views

Tryif (reset='1') theninstead

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