NIOS II design with TSEMAC and Embedded transceivers using Arria II GX/Stratix II GX

[Altera_Forum]

Hi, 

I have to design a gigabit ethernet interface using NIOS II , TSEMAC with the target device Arria II GX/Stratix II GX. But i don't find any reference design which gives an idea of how to integrate TSEMAC to the embedded tranceivers. Also i need to know if we use embedded transceivers then we don't have to use any PHY device external to FGPGA? The only external components would be the magnetics and the RJ45 connectors?  Also i would like to know how to configure the data rate we want? Unlike in external PHY 88E1111, there is no mention of AUTONEG and speed selection in emdedded transceivers... I understand that Arria II GX has data rate from 600Mbps to 3.75Gbps, but can we achieve 100Mbps fast ethernet by any technique?  Fast reply is highly appreciated as the requirement is urgent

[Altera_Forum]

The FPGA's transceivers are not really intended to drive ethernet cables. You can use the transceivers without a PHY but it would be primarily if you are driving ethernet between devices in a chassis, over board traces, or through a backplane. You might be able to drive some short cable lengths with the transceiver but it certainly wouldn't meet specifications. 

 What makes more sense for you is to use an external PHY that supports SGMII. Then use the FPGA's transceivers to communicate with the PHY via SGMII. This is definitely supported and there are several development boards available that would allow you to try out this scheme.  Jake