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NIOS TSE initialize

Altera_Forum
Honored Contributor II
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Dear All, 

 

I am new in NIOSII and TSE. I use the Altera developemnt DK-DEV-4CGX150N for project development. I use the Qsys to build up my system and want to write some code to make the development board to TX some data to my PC. 

 

I use a sniffer program to capture the data TX to my PC. In my current situation, I cannot receive any data at the PC. My program flow is as below: 

1. Hardware reset the PHY. 

2. Initialize the phy (mdio address, change to RGMII mode...) 

3. Software reset the TSE 

4. Setup those FIFO threshold of the TSE 

5. Disable both shift 16 for TX and RX 

6. Set the TSE CMD config to enable the TSE 

7. Set the MAC address of TSE 

8. Set up SGDMA device and descriptor 

9. Send data to my PC. 

 

I reference to the examplet program in following thread to build my program. But still not work. 

 

"tse mac and marvell 88e1111

 

I attached herewith is a few files of my design for your refrence. 

 

I believe that the issue is due to the initialize process of my TSE and phy. Would any one provide some advice on it. 

 

Thanks for your kind help in advance. 

 

Best Regards, 

Albert Siu
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Altera_Forum
Honored Contributor II
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First you must uncheck the "Ignore mismatched system ID" and "Ignore mismatched system timestamp" boxes. Those are very important to debug a problem such as yours, as it will ensure that your hardware and software configurations match. 

And in fact the warning on the top of your window (capture 1) seem to indicate that you have indeed a mismatch. Be sure that the FPGA has the correct configuration. You can follow the steps I gave in this message (http://www.alteraforum.com/forum/showthread.php?p=142260#post142260).
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Altera_Forum
Honored Contributor II
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I regenerate the QSYS, recompile the FPGA code, download the FPGA code. Then NIOS SBT still report that there is a timestamp error. As per the screen capture. Please provide some advice on how to fix this issue. Thx.

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Altera_Forum
Honored Contributor II
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It still means that the image uploaded into the FPGA isn't the one expected by SBT. Check again that you use the correct .sof file in the FPGA and that SBT points to the correct .sopcinfo file. 

Did you try to recompile the software too, after you compiled and uploaded the FPGA image?
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