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Native PHY IP Core - Clocking of separated rx/tx channels

Altera_Forum
Honored Contributor II
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Hi all ! First, i use Arria V GT.I try to make a simple loopback for 10G signal, and I use separated transmit and receive channels from Native PHY IP Core (simplified interface without reconfiguration).The question is how to combine the data from the receive channel with a transmission channel, even if they clocked by one reference signal (from onboard oscillator (~155,52 MHz)), its frequencies (rx_pma_clkout and tx_pma_clkout) may be different (not 0 ppm). So, as the tester can not see the frame synchronization, there is an error somewhere.Could somebody tell, do I have to use PLL IP Core (or it's not important), and how to properly connect the clock signals. Maybe I need to use some sort of compensation FIFO for valid data stream? Or I'm doing something very wrong. Please, help.This is my mapping in the attachment. Data_delay just transmit data to data_out with falling_edge(clk), it's for 0.5 cycle delay (it is written in some specification).

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