Hello!
I'm trying to simulate 6,4 Gb Native PHY channel between two fpga Arria V in Modelsim.
Cable length for physical channel must be is about 3 metres.
When I simulate delay in serial data path (in cable) between transceiver and receiver (two identical modules), receiver doesnt work and output CDR clock of the receiver isn't synchronized with input serial data.
When I synchronize input reference clock of the receiver with receiving data (by insertion delay which is the same as serial data delay), the receiver works properly,
but it's no good to match necessary phase reference clock for receiver in hardware. I think, Native PHY receiver must works independently of phase reference clock.
Could you please help me to solve this problem?
Screens with PHY settings
https://www.alteraforum.com/forum/attachment.php?attachmentid=8327 https://www.alteraforum.com/forum/attachment.php?attachmentid=8328
