FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

Native PHY Tranceiver Arria V. Problem with clock

Altera_Forum
Honored Contributor II
786 Views

Hello! 

I'm trying to simulate 6,4 Gb Native PHY channel between two fpga Arria V in Modelsim. 

Cable length for physical channel must be is about 3 metres.  

When I simulate delay in serial data path (in cable) between transceiver and receiver (two identical modules), receiver doesnt work and output CDR clock of the receiver isn't synchronized with input serial data. 

When I synchronize input reference clock of the receiver with receiving data (by insertion delay which is the same as serial data delay), the receiver works properly,  

but it's no good to match necessary phase reference clock for receiver in hardware. I think, Native PHY receiver must works independently of phase reference clock. 

Could you please help me to solve this problem? 

 

Screens with PHY settings 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8327 https://www.alteraforum.com/forum/attachment.php?attachmentid=8328
0 Kudos
0 Replies
Reply