Need help to read and write On-Chip Memory Mapped FIFO

Altera_Forum · ‎06-27-2012

Hello,

Currently I am working on DE2-115 Dev kit. I am using on chip memory mapped FIFO to write data into encoder and read data from the encoder. How to know the write address and read address of the FIFO_WRITE and FIFO_READ respectively.

FIFO_WRITE ==> ENCODER ==> FIFO_READ

(FIFO_0_IN) (FIFO_1_OUT)

API used to write and read FIFO:

=> int altera_avalon_write_fifo(alt_u32 write_address, alt_u32

ctrl_address, alt_u32 data)

=> int altera_avalon_fifo_read_fifo(alt_u32 read_address, alt_u32

ctrl_address)

Thanks for any suggestion and help.

Regards,

altera1085

//system.h

/*

* fifo_0_in configuration

*

*/

# define ALT_MODULE_CLASS_fifo_0_in altera_avalon_fifo

# define FIFO_0_IN_AVALONMM_AVALONMM_DATA_WIDTH 32

# define FIFO_0_IN_AVALONMM_AVALONST_DATA_WIDTH 32

# define FIFO_0_IN_BASE 0xb00d998

# define FIFO_0_IN_BITS_PER_SYMBOL 16

# define FIFO_0_IN_CHANNEL_WIDTH 8

# define FIFO_0_IN_ERROR_WIDTH 8

# define FIFO_0_IN_FIFO_DEPTH 16

# define FIFO_0_IN_IRQ -1

# define FIFO_0_IN_IRQ_INTERRUPT_CONTROLLER_ID -1

# define FIFO_0_IN_NAME "/dev/fifo_0_in"

# define FIFO_0_IN_SINGLE_CLOCK_MODE 1

# define FIFO_0_IN_SPAN 4

# define FIFO_0_IN_SYMBOLS_PER_BEAT 2

# define FIFO_0_IN_TYPE "altera_avalon_fifo"

# define FIFO_0_IN_USE_AVALONMM_READ_SLAVE 1

# define FIFO_0_IN_USE_AVALONMM_WRITE_SLAVE 1

# define FIFO_0_IN_USE_AVALONST_SINK 0

# define FIFO_0_IN_USE_AVALONST_SOURCE 0

# define FIFO_0_IN_USE_BACKPRESSURE 1

# define FIFO_0_IN_USE_IRQ 0

# define FIFO_0_IN_USE_PACKET 1

# define FIFO_0_IN_USE_READ_CONTROL 0

# define FIFO_0_IN_USE_REGISTER 0

# define FIFO_0_IN_USE_WRITE_CONTROL 1

/*

* fifo_0_in_csr configuration

*

*/

# define ALT_MODULE_CLASS_fifo_0_in_csr altera_avalon_fifo

# define FIFO_0_IN_CSR_AVALONMM_AVALONMM_DATA_WIDTH 32

# define FIFO_0_IN_CSR_AVALONMM_AVALONST_DATA_WIDTH 32

# define FIFO_0_IN_CSR_BASE 0xb00d900

# define FIFO_0_IN_CSR_BITS_PER_SYMBOL 16

# define FIFO_0_IN_CSR_CHANNEL_WIDTH 8

# define FIFO_0_IN_CSR_ERROR_WIDTH 8

# define FIFO_0_IN_CSR_FIFO_DEPTH 16

# define FIFO_0_IN_CSR_IRQ -1

# define FIFO_0_IN_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1

# define FIFO_0_IN_CSR_NAME "/dev/fifo_0_in_csr"

# define FIFO_0_IN_CSR_SINGLE_CLOCK_MODE 1

# define FIFO_0_IN_CSR_SPAN 32

# define FIFO_0_IN_CSR_SYMBOLS_PER_BEAT 2

# define FIFO_0_IN_CSR_TYPE "altera_avalon_fifo"

# define FIFO_0_IN_CSR_USE_AVALONMM_READ_SLAVE 1

# define FIFO_0_IN_CSR_USE_AVALONMM_WRITE_SLAVE 1

# define FIFO_0_IN_CSR_USE_AVALONST_SINK 0

# define FIFO_0_IN_CSR_USE_AVALONST_SOURCE 0

# define FIFO_0_IN_CSR_USE_BACKPRESSURE 1

# define FIFO_0_IN_CSR_USE_IRQ 0

# define FIFO_0_IN_CSR_USE_PACKET 1

# define FIFO_0_IN_CSR_USE_READ_CONTROL 0

# define FIFO_0_IN_CSR_USE_REGISTER 0

# define FIFO_0_IN_CSR_USE_WRITE_CONTROL 1

/*

* fifo_1_out configuration

*

*/

# define ALT_MODULE_CLASS_fifo_1_out altera_avalon_fifo

# define FIFO_1_OUT_AVALONMM_AVALONMM_DATA_WIDTH 32

# define FIFO_1_OUT_AVALONMM_AVALONST_DATA_WIDTH 32

# define FIFO_1_OUT_BASE 0xb00d99c

# define FIFO_1_OUT_BITS_PER_SYMBOL 16

# define FIFO_1_OUT_CHANNEL_WIDTH 8

# define FIFO_1_OUT_ERROR_WIDTH 8

# define FIFO_1_OUT_FIFO_DEPTH 16

# define FIFO_1_OUT_IRQ -1

# define FIFO_1_OUT_IRQ_INTERRUPT_CONTROLLER_ID -1

# define FIFO_1_OUT_NAME "/dev/fifo_1_out"

# define FIFO_1_OUT_SINGLE_CLOCK_MODE 0

# define FIFO_1_OUT_SPAN 4

# define FIFO_1_OUT_SYMBOLS_PER_BEAT 2

# define FIFO_1_OUT_TYPE "altera_avalon_fifo"

# define FIFO_1_OUT_USE_AVALONMM_READ_SLAVE 1

# define FIFO_1_OUT_USE_AVALONMM_WRITE_SLAVE 1

# define FIFO_1_OUT_USE_AVALONST_SINK 0

# define FIFO_1_OUT_USE_AVALONST_SOURCE 0

# define FIFO_1_OUT_USE_BACKPRESSURE 1

# define FIFO_1_OUT_USE_IRQ 0

# define FIFO_1_OUT_USE_PACKET 1

# define FIFO_1_OUT_USE_READ_CONTROL 1

# define FIFO_1_OUT_USE_REGISTER 0

# define FIFO_1_OUT_USE_WRITE_CONTROL 0

/*

* fifo_1_out_csr configuration

*

*/

# define ALT_MODULE_CLASS_fifo_1_out_csr altera_avalon_fifo

# define FIFO_1_OUT_CSR_AVALONMM_AVALONMM_DATA_WIDTH 32

# define FIFO_1_OUT_CSR_AVALONMM_AVALONST_DATA_WIDTH 32

# define FIFO_1_OUT_CSR_BASE 0xb00d960

# define FIFO_1_OUT_CSR_BITS_PER_SYMBOL 16

# define FIFO_1_OUT_CSR_CHANNEL_WIDTH 8

# define FIFO_1_OUT_CSR_ERROR_WIDTH 8

# define FIFO_1_OUT_CSR_FIFO_DEPTH 16

# define FIFO_1_OUT_CSR_IRQ -1

# define FIFO_1_OUT_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1

# define FIFO_1_OUT_CSR_NAME "/dev/fifo_1_out_csr"

# define FIFO_1_OUT_CSR_SINGLE_CLOCK_MODE 0

# define FIFO_1_OUT_CSR_SPAN 32

# define FIFO_1_OUT_CSR_SYMBOLS_PER_BEAT 2

# define FIFO_1_OUT_CSR_TYPE "altera_avalon_fifo"

# define FIFO_1_OUT_CSR_USE_AVALONMM_READ_SLAVE 1

# define FIFO_1_OUT_CSR_USE_AVALONMM_WRITE_SLAVE 1

# define FIFO_1_OUT_CSR_USE_AVALONST_SINK 0

# define FIFO_1_OUT_CSR_USE_AVALONST_SOURCE 0

# define FIFO_1_OUT_CSR_USE_BACKPRESSURE 1

# define FIFO_1_OUT_CSR_USE_IRQ 0

# define FIFO_1_OUT_CSR_USE_PACKET 1

# define FIFO_1_OUT_CSR_USE_READ_CONTROL 1

# define FIFO_1_OUT_CSR_USE_REGISTER 0

# define FIFO_1_OUT_CSR_USE_WRITE_CONTROL 0

Altera_Forum · ‎06-27-2012

The addresses are the _BASE constants. I'm guessing your write address is FIFO_0_IN_BASE, your write control address is FIFO_0_IN_CSR_BASE, your read address is FIFO_1_OUT_BASE and your read control address is FIFO_1_OUT_CSR_BASE.

Altera_Forum · ‎06-27-2012

First of all thanks for the reply. I have already tried with these write and read addresses. The data is not shown at write address. second thing is that the FIFO fill level is not incremented.

In read operation, read back value is always -1 which is wrong. READ FIFO fill level is also not decremented.

FIFO depth is 16. FIFO_0_IN =>address range 0xb00d998 - 0xb00d99b

FIFO_1_OUT => address range 0xbd0099c - 0xb00d99f

Regards,

altera1085

Altera_Forum · ‎06-29-2012

Are you sure the correct .sof file is uploaded in the FPGA first? Are you using the system ID component to ensure that?

Could you show the C code you are using?

Altera_Forum · ‎06-29-2012

Thanks for the replay..

Now I have bypassed the encoder and FIFO_0 directly connected to FIFO_1. I can write the data into FIFO_0 and read the data from the FIFO_1 successfully. Only Encoder is the problem.

settings:

FIFO_0 :

input => AVALONMM WRITE

output => AVALONST SOURCE

FIFO_1:

input => AVALONST SINK

output => AVALONMM READ

Which are the signals are necessary to read from the FIFO_0 and write to FIFO_1.

Regards,

altera1085

Altera_Forum · ‎07-02-2012

To debug your system you should put some signaltap probes on your encoder avalon stream inputs and outputs and see what is happening.

What kind of encoder is it?