Nios+PCI doesn't work together, help.

[Altera_Forum]

I create Nios+PCI compiler (PCI target 32-bit) system on Cyclone II. When PCI is connected, Nios doesn't load any software, but works good without PCI. I've made PCI in reset, without clk - doesn't help. 

 What I can do else? What is the problem? :confused:

[Altera_Forum]

I'm using both PCI Master-target 32 bit 33MHz and Nios II in my design. How you connect your PCI component and NIOS II in your SOPC? What is your PCI Clock/Reset Setting? Did you assign your reset address correctly?

[Altera_Forum]

I moved Nios to 33MHz (from 66) and it started working good.

[Altera_Forum]

Do you use the pci mt32 core ? I use it with the "user guide" saied,(by the way,which is with the sopc builder flow) but in the PC ,can not find the pci device, 

before, I used the pci t32 connected to sdram with the sopc builder flowing ,it worked well. can you help me?  thank you

[Altera_Forum]

I use pci_t32. Does your pci_t32 working well on this board?

[Altera_Forum]

yes ,pci t32 works well ,but pci mt32 can not . I do not known what is worry with it.

[Altera_Forum]

Try to localize the problem. For example: 

1.Connect SignalTap to PCI IO on fully working FPGA, and compare bus configuration cycle with PCI standard. 2.Disconnect PCI from IO pad, connect to FPGA via JTAG and find out, does PCI IP core is working. 3.Check out the state of master-mode only PCI signals (REQ,GNT and so on).  Or ask this question to mySupport at Altera.

[Altera_Forum]

by the way ,I find my pci t32 ip can not support brust transaction, PC read some words from sdram which connect to the pci ip , in SignalTap I find the PC read word one by one . that is so slowly. 

at last I find "Reads originated from an x86 (Intel) architecture CPU destined to a PCI slav e device (such as PLX 9050) will never be bursted. This is a x86 IA32 limita tion."  this is the addr of this words http://learn.tsinghua.edu.cn:8080/2004210935/bm/csarch2000-4100/1368.htm   I do not known whether your pci t32 has this condition or not.

[Altera_Forum]

by the way ,I find my pci t32 ip can not support brust transaction, PC read some words from sdram which connect to the pci ip , in SignalTap I find the PC read word one by one . that is so slowly. 

at last I find "Reads originated from an x86 (Intel) architecture CPU destined to a PCI slav e device (such as PLX 9050) will never be bursted. This is a x86 IA32 limita tion." this is the addr of this words http://learn.tsinghua.edu.cn:8080/20...-4100/1368.htm (http://learn.tsinghua.edu.cn:8080/2004210935/bm/csarch2000-4100/1368.htm)  I do not known whether your pci t32 has this condition or not.