- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Short of re-spin of the board, can I 1) use the x4 Avalon-MM DMA and only connect x1? or 2) is there an example design that utilizes the DMA_Controller IP or similar with the PCIe IP?
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Sir, it is true that you need x4 lane for PCIE AVMM DMA. The x1 will not work because it unable to meet the bandwidth requirement that need from the DMA. conclusion is you might still see the LTSSM is work, but memory transfer will fail.
You may get the reference design from this AN:-
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an690.pdf

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page