OpenCore [I2C_Master_Slave] _Newbie

Altera_Forum · ‎07-25-2008

I am a newbie.

I download I2C_Master_Slave ip core from OpenCore web site.

Then I inport to QuartusII Web Edition,then compiler,I got the error message,below.

"Error (10207): Verilog HDL error at tst_bench_top.v(242): can't resolve reference to object "wb_write"

I read help files.QuartusII Wed Edition support hierarchical node name.

Could someone tell me where are errors.

Program division:

[tst_bench_top.v]

// hookup wishbone master model

wb_master_model# (8, 32) u0 (

.clk(clk),

.rst(rstn),

.adr(adr),

.din(dat_i),

.dout(dat_o),

.cyc(cyc),

.stb(stb),

.we(we),

.sel(),

.ack(ack),

.err(1'b0),

.rty(1'b0)

);

// program internal registers

u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte

//Error

u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte

u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte

[wb_master_model.v]

module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);

task wb_write;

input delay;

integer delay;

input [awidth -1:0] a;

input [dwidth -1:0] d;

begin

// wait initial delay

repeat(delay) @(posedge clk);

// assert wishbone signal

# 1;

adr = a;

dout = d;

cyc = 1'b1;

stb = 1'b1;

we = 1'b1;

sel = {dwidth/8{1'b1}};

@(posedge clk);

// wait for acknowledge from slave

while(~ack) @(posedge clk);

// negate wishbone signals

# 1;

cyc = 1'b0;

stb = 1'bx;

adr = {awidth{1'bx}};

dout = {dwidth{1'bx}};

we = 1'hx;

sel = {dwidth/8{1'bx}};

end

endtask

Altera_Forum · ‎07-25-2008

I have got the VHDL version of this i2c master open core working as a NIOS component.

I am not sure why you have the problem.

I found the following posts useful when I was trying to get it working

http://www.nabble.com/i2c-and-avalon-bus-td17530366.html

http://forum.niosforum.com/forum/lofiversion/index.php/t3583.html

Altera_Forum · ‎07-25-2008

Here is the issue I2C core.

http://www.turboupload.com/download/nzvmqjskhalq/i2c.zip (http://www.turboupload.com/download/nzvmqjskhalq/i2c.zip)

Could someone find the issue?

Thanks.

Altera_Forum · ‎07-26-2008

It seems that you try to compile test bench/reference model file(s), which could not be synthesized in Quartus.

Altera_Forum · ‎07-29-2008

Testbench needed ModelSim to parse,not in Quartus.