Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
780 Views

Output Latency for Integer Arithmetic Megacore at Cyclon Family

I do not know what Output Latencies are valid for a Cyclon V Device for the Interger Arithmetic Megacore Functions, so I used the worst case values I found in the User Guide for pipelining the functions.  

Has anybody some hints, how I can find out the correct / optimized values for the Cyclon Family?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
30 Views

 

--- Quote Start ---  

I do not know what Output Latencies are valid for a Cyclon V Device for the Interger Arithmetic Megacore Functions, so I used the worst case values I found in the User Guide for pipelining the functions.  

Has anybody some hints, how I can find out the correct / optimized values for the Cyclon Family? 

--- Quote End ---  

 

 

pipelining the core is not matter specific to a device. You have options of pipeline from 0 to whatever and you choose whatever helps your design achieve speed. If you start with a pipeline of 1 and it failed timing at the core then go up to 2 and so on.