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Altera_Forum
Honored Contributor I
871 Views

Output of lpm_divide is x's when inputs are 0 in modelsim

I am doing simulations in a design that uses the lpm_divide megafunction. I noticed that I am having issues since the output of lpm_divide is x's (for both outputs) when the inputs are 0. Is there any way to change the output to 0 without causing any additional latency?

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Altera_Forum
Honored Contributor I
28 Views

Although zero divide by zero is mathematically NAN (not-a-number), a parallel divider should give a defined '0'/'1' bit vector.  

 

I don't see a reason to expect an all '0' output.  

 

The MegaFunction user manual specifies 'x' output for divide by zero. I think, this means it's up to the synthesis tool optimization to make individual bit either '0' or '1'. The simulator is apparently reflecting this ambiguity, you should run a gate level simulation to see the actual output. Forcing zero output for divide by zero requires additional logic anyway.
Altera_Forum
Honored Contributor I
28 Views

I can't test it with gate-level simulation so I have to use RTL. Since timing is not even checked in RTL, I guess that I could add that extra logic in since it won't affect anything until I actually compile the design.

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