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Altera_Forum
Honored Contributor I
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PCI-E IP Core Simulation

After I generate PCI-E IP core root port in QuartusII 9.1 SP2 , How can I start Medelsim function simulation? 

I mean that which files should be added into the simulatin project? 

BTW: under my project folder, there are following folders: 

\db 

\work 

\pci_express_compiler-library 

\pcie_core_examples\common\testbench 

.................\incremental_compile_module 

.... \rootport\db 

..................\testbench 

 

Should I add copy all files under \rootport\testbench\ and \common\testbench\ to single fold?
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