Hi,We have a Bittware PCIe card with a Stratix V FPGA. What is the best way to get started using this board to communicate with other devices on the PC via PCIe? I have looking looking at "Stratix V Hard IP for PCI Express user guide" and other documents but there is too much information and I can not seem to find a simple example of how to build a project that does something via PCIe. How would I go about programming the FPGA to access my computer's RAM for example via PCIe? Any help would be much appreciated. Thanks in advance.
The simplest, but also most "underpowered" PCIe implementation is to use the Qsys component.This thread has a link to a PDF showing how to create the PCIe end-point under an earlier version of Quartus. The steps should be the same under 14.0, or at least very similar. http://www.alteraforum.com/forum/showthread.php?t=35678 If there is something that does not make sense to you in that document, let me know, and I'll try to explain. I don't have a Stratix V board, so cannot give you a working example, but can try to help. Which board do you have? http://www.bittware.com/products-services-fpga-cots-hardware-fpgatype/altera-stratix-v-fpga Cheers, Dave
I agree with Dave on QSYS.I have run the Stratix V Kit card running several designs with DMA and NIOS .... I am currently working with Arria V and Cyclone IV kit cards. Possibly I can go back to see if I have something that worked on Stratix V. From my experience the main issue was developing a Linux DD for the application I had since I was focused on Linux systems. If you are in the Windows world, there is some support for PCIe drivers in the examples. I have found 3 problems related to execution ... 1. The documentation is good but as you indicate somewhat scrambled on how to find it . There needs to be a more intelligent search engine maybe within Altera to generate results based on the documentation out there. 2. On the kits and example applications, it seems there are sample applications but often they need conversion to the FPGA family of interest. Also, the kits may have been developed including BTS and examples with a previous development system and now QSYS seems to be they way and I can't easily run the examples that came with the kit. 3. For PCIe , the HARD IP core is configured as a Megafunction or similar and I have not been successful in running the Megafunction editor or PCIe IP compiler to fine tune the IP. Best Regards, Bob.
Hi, and thanks for the replies.The name of the board is S5-PCIe-HQ. I am attempting the example on the PDF on how to create the PCIe end-point using Quartus 14.0 and on Ubuntu 12.04. I am having problems when it comes to adding the ALTPLL and other components as the MegaWizard plug-in manager does not exist on 14.0 it seems. I have read that it is replaced by Ip Catalog , but when I try to use that , it does nothing. Any suggestions? How exactly does the Avalon MM Base Address Registers work. I am trying to fully understand. For example, to get the board to access my computer's RAM via PCIe, must I put the RAM address there? or If I wish to talk to another PCIe device on my computer, how does it work? Thanks again for your help.
Hi Mulligan.1. On the Quartus 14.1 I have no experience ... it may work better to load 13.1 if that works better with the examples you have or contact Altera or post in t forums section for tools. 2. I checked S5-PCIe-HQ and it looks like quite a nice card since it supports a variety of Stratix devices and runs up to Gen3 speed. 3. On the basics of how to communicate host -> endpoint and endpoint -> host memory, let me point you to a .pdf that I believe does a fairly good job of describing both directions. I have attached images of the figures thatI found useful. Seatch for this .pdf "IP Compiler for PCI Express User Guide" by Altera. The attached images are from that document. Ideally, start with an example design and expand from there. In summary, to transfer data from your host system ( RC ) to the endpoint, your device driver will first discover the endpoint, assign system memory to the endpoint when the device driver is installed. At this point, memory writes / reads to the assigned address regions will be claimed by the endpoint BAR comparitors and delivered to some slave device behind the endpoint PCIe core. Conversly, for the endpoint card to DMA data to the host system, there is a translation mechanism that translates an internal address to a 32 or 64 bit PCIe address and the write or read transaction ends up at the host system as a memory write or read. Normally the device driver would manage the DMA buffer allocation in the host system ( Linux ) where the physical bufffer address is known by the endpoint card for the DMA and the corresponding virtual address is known by the process running Linux. On the subject of an endpoint communicating with another PCIe endpoint, that would involve a PCIe switch , and I am not familiar with systems ( with PCIe slots ) that support endpoint to endpoint connections via a PCIe switch on the host system board ... however they may exist. Best Regards, Bob.
--- Quote Start --- I have read that it is replaced by Ip Catalog , but when I try to use that , it does nothing. Any suggestions? --- Quote End --- It works fine for me. When you click on Tools->IP Catalog a new window is displayed in the main GUI. From within that window you can select the IP core just as you would have with the old MegaWizard. Cheers, Dave
For some reason, when I open Tools->IP Catalog, nothing happens. I am following instructions from the PDF that you linked me to before : "Altera PCIe Analysis" when trying to add the ALTPLL component. This design example is for the Stratix IV tho. I am trying to get some example working here for Startix V. Cheers
--- Quote Start --- For some reason, when I open Tools->IP Catalog, nothing happens. --- Quote End --- Try View->Utility Windows->IP Catalog --- Quote Start --- I am following instructions from the PDF that you linked me to before : "Altera PCIe Analysis" when trying to add the ALTPLL component. This design example is for the Stratix IV tho. I am trying to get some example working here for Startix V. Cheers --- Quote End --- It should work for Stratix V too. Hopefully Altera has kept the IP Catalog interface the same as the older MegaWizard version (they have for the other parts I've been using). Cheers, Dave
Thanks Dave,I've managed to add the components now. The example will not compile for me however. I am getting error "SystemVerilog error at qsys-top.sv(267) : can't resolve implicit port connection(s) to instance ""u4" without a module declaration or an extern equivalent" and I have followed all the instructions carefully on that PDF on how to create the PCIe end-point. This design example is for Stratix IV and I am trying to compile for Stratix V. Is that the issue here? We seem to have hit a brick wall here and are struggling to get an example working on Stratix V. There are plenty of documents showing how to use QSys to generate the PCIe hard IP for Stratix V but not on how to use it. Cheers, Paul
Hi Paul,--- Quote Start --- The example will not compile for me however. I am getting error "SystemVerilog error at qsys-top.sv(267) : can't resolve implicit port connection(s) to instance ""u4" without a module declaration or an extern equivalent" and I have followed all the instructions carefully on that PDF on how to create the PCIe end-point. This design example is for Stratix IV and I am trying to compile for Stratix V. Is that the issue here? --- Quote End --- Most likely. You need to look at the top-level component generated by the Qsys system. The ports on that component instance need to match whatever is instantiated in the top-level design. I suspect that the PCIe interface ports changed slightly between the Stratix IV and V, and you simply need to correct for those differences. --- Quote Start --- We seem to have hit a brick wall here and are struggling to get an example working on Stratix V. There are plenty of documents showing how to use QSys to generate the PCIe hard IP for Stratix V but not on how to use it. --- Quote End --- The wall you have hit now is really just understanding how to debug HDL code. Open up Qsys and look at the "HDL Example" it produces, and then check that the ports match the instance. Cheers, Dave
Hi everybody,I`m new on this forum and in the usage of Altera product, then be patients please. In 2 days of research, I`m not able to find the answer to my questions. I want read and write from my FPGA (Stratix V) to the Host PC RAM, using PCIe bus, without involve the CPU (like mulligan252). In the specific, FPGA writes in RAM and when the data transfer is finished, FPGA sends an interrupt to the CPU. When CPU receives the interrupt from the FPGA, reads data from PC RAM. In this thread is described how the FPGA side can be realized. My questions are: how can I realize the PC communication side? Is there some driver, API or library to do that? where can I find them? Thanks you very much Federico