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PCI express and fixed address translation table

Honored Contributor II

We are using UIO for Linux 




In conjunction the Cyclone IV transceiver starter kit to access Avalon peripherals, over the PCI express interface, to a x86 board running Linux.  


This has been great and relatively easy when the x86 has been initiating the transactions (BAR + Offset to peripherals including on chip ram). So far so good.  


However now I want a custom peripheral to access the memory on the x86 side, note, the peripheral works fine when it accesses the memory on the FPGA.  


First of all we used mem at Linux boot up to reserve a 1M block of memory at physical address 0x10000000. 


In the grub.cfg file I set 




I set a fixed address translation table with two address pages to 


Page 0 – PCIe address 63:32 to 0x00000000, PCIe address 31:0 to 0x10000000 

Page 1 - PCIe address 63:32 to 0x00000000, PCIe address 31:0 to 0x00000000 


The address of the memory mapped slave txs on Qsys is 0x04000000.  


The start address of the peripheral writes to and then reads from is set to 0x04000000.  


The peripheral then runs and on signal tap I can see Avalon Master addresses in the range 0x04000000 to 0x0403FFFF with data being written and read.  


However when I check the physical memory address range above 0x01000000 on the x86 board the memory does not change. Therefore the registers offset from the BARs are being written but the x86 memory is not changing.  


I am using the 11.1 tools. (Quartus, Signaltap II and Qsys). 


Any ideas?  


Thank you for reading.
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2 Replies
Honored Contributor II

I met exact same problem as you. Have you solved it?

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Honored Contributor II


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I met exact same problem as you. Have you solved it? 

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We stopped using UIO and switched to using PCI kernel drivers.  



Start with this an build.  


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