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PCI interrupt problem

Altera_Forum
Honored Contributor II
1,206 Views

Hi 

 

I'm developing a project with altera FPGA cyclone IV Development Board connected to a PC via PCIe bus. I'm trying to generate a PC Interrupt when a push button of the dev board is pressed. 

I use Quartus 2 Version 12.1 and Qsys tool , the top entity is written in verilog.  

In Qsys I have connected the PCIe IP with an onchip_memory and a PIO avalon interface, the bar are configurated in this way: 

 

bar 0 (32 bit not prefetchable) 0x00000000 0x00003fff onchip_memory || 0x00004000 0x00007fff cra register 

bar 1 (32 bit not prefetchable) 0x00000000 0x00003fff PIO  

 

the interrupt signal of the PIO module is connected with the RXmIrq0 of the PCIe 

The PCIE ip compiler is configurated : 

  • number of lane 1 

  • completer only 

  • ref clock 100Mhz 

 

 

 

I have some questions : 

  1. it's possible to check if the interrupt signal is generated by the PIO module, for example by blinking a led? 

  2. I succedded in reading and writing the on_chip_memory with a custom wince driver but this driver doesn't capture the interrupt signal. The status register at address 0x40 of the CRA is always 0 , what I have to check ? 

  3. The windows driver must clear the interruptmask register of the PIO interface and also the PCIE interrupt status register ? 

  4. What is the Address Translation Table of the CRA ? 

 

 

I'm sorry for the number of questions , I'm newbie in FPGA system ....
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2 Replies
Altera_Forum
Honored Contributor II
56 Views

You may needs configure the pcie core as Requester/Completer instead of Requester-only.ost 

In Completer-only mode, the IP Compiler for PCI Express can receive requests, but cannot initiate upstream requests, this will cause the MSI interrupt not reach the host side. 

 

For more info about MSI Interrupts Handling, refer to http://www.alterawiki.com/wiki/handling_pcie_interrupts
Altera_Forum
Honored Contributor II
56 Views

Try configure the PCIe core to requester/completer instead on completer-only. 

Completer-Only mode only can receive requests, but cannot initiate upstream requests.
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