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I am using Stratix10 PCIE IP
I change to a newer Quartus version 19.4 pro and I found there is additional input signal for this IP. The signal name is ninit_done. Where should I connect this signal?
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Hi,
You can find the ninit_done signal (output signal) from the Reset Release Intel FPGA IP. You need to instantiate this IP in your design to reset the user logic.
Regards -SK

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