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I created a PCIE Gen3 x8 AVLMM design for Arria 10 GX dev kit. I am facing problem to assign the pin location assignment for the TX and RX pin. Do you have the TX/RX pin location assignment for the dev kit? TQ
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Hi Sir,
There are fews PCIe designs targeting the A10 GX Dev kit from design store.
https://fpgacloud.intel.com/devstore/platform/?acds_version=any&ip_core=PCIExpress&family=arria-10&board=14

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