- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Is the PCIe Avalon-MM implementation limited to 64 bit transfers? I'm not seeing the PCIe IP use the Avalon byteenables correctly to size the transfer. Is the IP limited to only supporting 64-bit accesses?
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Did you ever figure this out, I am wondering this myself. I am having a problem because it accesses a register that triggers an event on a read.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page