I'm trying to set up a Qsys design using the PCIe core on an Arria II GX, and running into some problems. First of all, half of the documentation my version of the IP Compiler for PCI Express User Guide (May 2011) seems to be out of date in Quartus 12.1. Is there any newer documentation than this now two year old one?
Secondly, I'm being told by Qsys that, contrary to the documentation, there's no ability to generate a VHDL testbench or simulation. I checked the installed directory, and there's no match for altpcietb_bfm*.vhd. Has Altera really entirely dropped VHDL support from the toolchain? I've already found that asking Qsys to generate VHDL for synthesis is a mistake; it generates mismatched buses that throw compile errors. Is Altera no longer committed to supporting VHDL users?
Finally, when I broke down and decided I'd just generate it all in Verilog and try to put some wrapper functions around it myself, I got the error message
Error: pcie_hip_pcie_bfm_0: add_fileset_file: No such file /home/rgaddi/altera/12.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.v while executing
"add_fileset_file altpcietb_bfm_driver.v VERILOG PATH $QUARTUS_ROOTDIR/eda/sim_lib/stratixiv_hssi_atoms.v "
(procedure "proc_sim_verilog" line 7)
invoked from within
"proc_sim_verilog altera_pcie_bfm"
Anyone know what to do with this?
