I need to use the Stratix5 FPGA as PCIe Gen3 endpoint on one side and SPI ROM interface on the other side. Normally in x86 PC architecture, the southbridge SPI rom interface integrated but I need to eliminate the southbridge ASIC and replace it with Stratix5 FPGA for ease in configuration and programmability. Here is the topology
X86 CPU ---> PCIe Gen3 Bus ---> Straitx5 EP ---> SPI Bus ----> SPI ROM
In this mode, the X86 CPU will generate a cycle right out of reset and we will gurantee that the request reaches to Stratix5 Endpoint. But I am not sure if the Straitx5 endpoint will be able to claim the cycle. As per my understanding, the Stratix5 endpoint will claim the cycle only if the BAR registers are set. This requires PCI configuration that is not run right at reset. How to enable all the transactions FROM X86 cpu to FPGA endpoint?
Is there a design I can leverage where southbridge fucntionlity is integrated in the FPGA? If so, it will be very useful.
Thanks.
CP
